1. Technical Field
The present invention generally relates to a semiconductor circuit, and more particularly, to an on-die termination circuit and a termination method.
2. Related Art
With technological advancements, such as DDR, DDR2, DDR3 and the like, many functions are added to semiconductor circuits, and especially, to semiconductor memory circuits.
In addition, as the functions are added, control circuits for controlling the respective functions and numerous signals are added.
Such signal addition causes an addition in a global line which is disposed over the entire circuit area, and such an addition in the global line is also applied to on-die termination circuits.
As illustrated in FIG. 1, a conventional on-die termination circuit 1 includes an impedance adjustment unit 10, a plurality of DQ circuit blocks 20, a DQS circuit block 30, a DQSB circuit block 40, and a plurality of global lines 50.
The impedance adjustment unit 10 generates a first impedance adjustment signal OCDT_DQ<0:2> and a second impedance adjustment signal OCDT_DQS<0:2> in response to a write leveling signal WTLEV, impedance setup signals Ron and RTT, a read command Read, an on-die termination command ODT, and a dynamic on-die termination command DODT.
In this case, the first impedance adjustment signal OCDT_DQ<0:2> is used to adjust the impedances of the DQ pads of the DQ circuit block 20.
The second impedance adjustment signal OCDT_DQS<0:2> is used to adjust the impedances of the DQS pad of the DQS circuit block 30 and the DQSB pad of the DQSB circuit block 40.
The DQ circuit block 20 adjusts the impedance of the DQ pad in response to the first impedance adjustment signal OCDT_DQ<0:2> and the write leveling signal WTLEV.
The DQS circuit block 30 adjusts the impedance of the DQS pad in response to the second impedance adjustment signal OCDT_DQS<0:2> and the write leveling signal WTLEV.
The DQSB circuit block 40 adjusts the impedance of the DQSB pad in response to the second impedance adjustment signal OCDT_DQS<0:2> and write leveling signal WTLEV.
The plurality of global lines 50 includes six global lines for separately transmitting the first impedance adjustment signal OCDT_DQ<0:2> and the second impedance adjustment signal OCDT_DQS<0:2>, and one global line for transmitting the write leveling signal WTLEV.
Hereinafter, the termination operation of the conventional on-die termination circuit will be described with reference to FIG. 2.
When an on-die termination command ODT (or Dynamic ODT) is activated (On-Die Termination Operation), a first impedance adjustment signal OCDT_DQ<0:2> and a second impedance adjustment signal OCDT_DQS<0:2> have the same setup value.
Accordingly, the impedances of a DQ pad and a DQS pad (DQSB pad) are adjusted to the same value, that is to say, to an RTT.
When a read command Read is activated (Read Operation), the first impedance adjustment signal OCDT_DQ<0:2> and the second impedance adjustment signal OCDT_DQS<0:2> have the same value.
Accordingly, the impedances of the DQ pad and the DQS pad (DQSB pad) are adjusted to the same value, that is to say, to 34Ω (or 45Ω).
Depending on the value H or L of the impedance setup signal Ron, the value of the first impedance adjustment signal OCDT_DQ<0:2> can vary. In this case, the value of the second impedance adjustment signal OCDT_DQS<0:2> varies to the same value as the first impedance adjustment signal OCDT_DQ<0:2>.
That is to say, when Ron=H, the first impedance adjustment signal OCDT_DQ<0:2> and the second impedance adjustment signal OCDT_DQS<0:2> can have the value of H, H, and H.
Additionally, when Ron=L, the first impedance adjustment signal OCDT_DQ<0:2> and the second impedance adjustment signal OCDT_DQS<0:2> can have the value of H, L, and H.
Therefore, the DQ pad and DQS pad (DQSB pad) can be adjusted to 34Ω when Ron=H, and the DQ pad and DQS pad (DQSB pad) can be adjusted to 45Ω when Ron=L.
Additionally, when a write leveling signal WTLEV is activated (Write Leveling Operation), the first impedance adjustment signal OCDT_DQ<0:2> and the second impedance adjustment signal OCDT_DQS<0:2> have mutually different values.
That is to say, similarly to the read operation, the first impedance adjustment signal OCDT_DQ<0:2> can have the value of H, H, and H when Ron=H, and can have the value of H, L, and H when Ron=L.
Accordingly, the DQ pad can be adjusted to 34Ω when Ron=H, and the DQ pad can be adjusted to 45Ω when Ron=L.
Additionally, the second impedance adjustment signal OCDT_DQS<0:2> has a setup value, like on an on-die termination operation, so that the impedance of the DQS pad (DQSB pad) is adjusted to an RTT.
In this case, the write leveling operation is an operation for compensating for a mismatch of signal levels in a write operation, and can be performed according to a command of a controller which controls a semiconductor device.
As seen by FIG. 2, in a write leveling operation, the values of the first impedance adjustment signal OCDT_DQ<0:2> and the second impedance adjustment signal OCDT_DQS<0:2> are set to values different from each other.
Therefore, the conventional technique uses a total of seven global lines 50 (see FIG. 1, (#7)) on the assumption that each of the first impedance adjustment signal OCDT_DQ<0:2> and the second impedance adjustment signal OCDT_DQS<0:2> is configured with 3 bits.
That is to say, six global lines for separately transmitting the first impedance adjustment signal OCDT_DQ<0:2> and the second impedance adjustment signal OCDT_DQS<0:2>, and one global line for transmitting a write leveling signal WTLEV are required.
As described above, according to the conventional technique, the number of global lines disposed over the entire circuit area increases to support an on-die termination function including a write leveling, so that net die decreases.